Current mode switching circuit



United States Patent [72] Inventor EdwlnK.C.Yu Norrlstown, Pa. [21]Appl.No. 627,491 [22] Filed Mar.31, 1967 [45] Patented Dec. 22, 1970[73] Assignee RCA Corporation a corporation of Delaware [54] CURRENTMODE SWITCHING CIRCUIT 4 Claims, I Drawing Flg.

[52] U.S.Cl. 307/215, 307/218 [51] Int. Cl ..1I03k 19/00 [50]FleldofSearch 307/239, 259, 214, 215, 218, 254; 328/98, 213; 330/30D, 19

[56] References Cited UNITED STATES PATENTS 3,182,210 5/1965 Jebens307/254 3,229,217 l/l966 Van Zeeland 330/18 3,259,761 7/1966 Narud et al307/214 3,263,091 7/1966 Cole et a1 307/254 3,392,346 7/1968 Staubus330/30D 3,417,262 12/1968 Yao 307/215 3,431,505 3/1969 DAgostino330/301) Primary Examiner-Donald D. Forrer Assistant Examiner-B. P.Davis Attorney-John V, Regan ABSTRACT: Current mode switching circuitshaving dual output emitter-follower output transistors are described.Power dissipation is considerably reduced by switching a common loadcurrent path from one to the other output terminal as determined by thebinary significance of the digital input signals, whereby the emittercurrent of only one of the emitter-follower transistors flows throughthe common path under steady state conditions.

, 1 1 cunrwur ona swrrcnnvc cmcurr BACKGROUND OF THE INVENTION Currentmodeswitching circuits are well suited for high speed .digital systems,for example electronic computers and other electronic apparatus, sincethetransistors therein can be operated out of saturation with'relativelysmall voltage swings, which may be on the order of a fraction of a voltor so. The avoidance of transistor saturation and the small voltageexcursioi'is enable current mode switching circuits to have a high speedof response. J Y

Que knowntypeof current mode switching circuit includes at least twotransistors having 'separate'collector circuits and a common emittercircuit" in which a current source'isconnected. The current source maybe simulated by a source of operating potential and a common signalcurrent path, such as a resistor. The current source current can berouted through either one of the alternate current paths provided by thecollector-to emitter paths of the transistors by application of asuitable differenceinpotential between the base electrodes thereof. Whenthis type of current mode switching circuit is utilized as a logic gate,the difference in potential is achieved by applying relatively high (H1)and relatively low (LO) binary signal voltage levels to one transistorbase electrode and a reference voltage (V to the othertransistor baseelectrode. A value intermediate the H1 and LO signallevels is assignedto V,-,.;, so that the potential difference between the two signallevels and V5,, controls which of the transistors the currerit is routedthrough. This type of logic gate is sometimes called a current modelogic (CML) gate.

lit the usual type CML gate complementary outputs are taken from thecollector electrodesof the two transistors. Each of the complementaryoutputs is often buffered by a separate emitterfollower (commoncollector) transistor. The dual emitter-follower transistors provide theCML gate with a low output impedance and provide signal level shift sothat the output signal levels are of the same digital voltage levels asthe binary input signals. Thus, the output terminals of one CML gate maybe directly connected to the input terminals of not only one other CMLgate, but also, due to the low output impedance, to the input terminalsof several other CML gates.

Although the dual output emitter-follower transistors provide the,aforementioned benefits, they also account for about two-thirds of thepower dissipation in the CML gate. Although power dissipation isgenerally undesirable, it is particularly so when the CML gatesarefabricated as integrated circuits wherein the dissipated heat can causeserious performance degradation. The present invention is directed tohovel improvements in CML gates whereby the power dissipation in theoutput emitter followers is reduced by a factor of one-half.

BRIEF SUMMARY or INVENTION According to the invention, a current modelogic circuit as described above is improved by providing a load currentswitch means. The load current switch means responds to one binary inputsignal condition to connect a common load current path to one of theoutput terminals and responds to a different input signal condition toconnect the common load current path to the other output terminal. Thus,the emitter current of only one of the dual emitter-follower outputtransistors flows through the common load current path under steadystate conditions.

According to the illustrated example of the invention, the load currentswitch means is comprised of a pair of transistors having their emitterelectrodes connected to the common load current path, their collectorelectrodes connected to different ones of the output terminals, andtheir base electrodes connected to the emitter electrodes of the twotransistors which comprise the input signal current switch. Diodeisolating means is provided toconnect the emitter electrodes of thesignal current switching transistors to their associated common signalcurrent path.

DESCRIPTION OF PREFERRED EMBODIMENTS Current mode switching circuitsaccording to my invention may be constructed either with discretecomponents or by means of integrated circuit processes. As used herein,the term, integrated circuit" refers to those technologies by which anentire circuit can be formed as by diffusion or by films in or on one ormore chips of materials such as silicon. Current mode switching circuitsaccording to the present invention may either be fabricated on separatechips or fabricated in combination with other circuitry in or onthe samesubstrate. As the case may be, the integrated circuit structures orchips so formed are usefulas building blocks which may be interconnectedand combined with appropriate power supplies and signal sources to formvarious systems.

Referring now to the sole FIG. of the drawing, there is shown generallyat 10 a current mode switching circuit according to the inventionwherein transistors 11 and 12 comprise an input signal current switch,while transistors 13 and 14 comprise an output or load current switch.The input signal switching transistors 11 and 12 have their collectorelectrodes 11c and 12c connected to a first supply connection 21 viacollector resistors 17 and 18, respectively The emitter electrodes Heand 12e are' connected via isolating devices, such as diodes 23 and 24,respectively, to a common signal current path, illustrated as an emitterresistor 19. The other end of .common emitter resistor 191s connectedto'asecond supply connection22. The base electrode 12b is connected to aterminal 27, to which isapplied a fixed reference voltage V,,.,; whilethe base electrode 11b is connected to receive binary input signals B.

Additional inputs to the current mode switching circuit may be providedby connecting the collector and emitter electrodes of additionaltransistors in parallel with the collector electrode and emitterelectrode llle of transistor 11. For example, as illustrated by thedashed connections, further transistor 31 has its collector electrode310 connected to the collector electrode 11c and its emitter electrode3le connected to the emitter electrode lle. The base electrode 31b isconnected to receive further binary input signals A.

The collector electrodes 11c and of the input signal current switch arefurther connected to the base electrodes 15b and 16b of dual outputemitter-follower output transistors 15 and 16, respectively.TransistorslS and 16 have their collector electrodes 15c and 160connected to supply connection 21 and their emitter electrodes 15c and16:: connected to output terminals 25 and 26, respectively, at whichcomplementary output signals C and C i are developed.

The output or load currentswitching transistors 13 and 14 have theircollector electrodes 13c and connected to output terminals 25 and 26,respectively, and their emitter'electrode 13c and 14e connected togetherand via a common load current path, illustratedas an emitter resistor 20to thesecond supply connection 22. Transistors l3 and 14 have their baseelectrodes 13b and l4b connected to the emitter electrodes 11e, 12e oftransistors 11 and 12, respectively.

A suitable source 55 of operating voltage of value E is connectedbetween the supply connections 21 and 22. For the illustrated NPN-typetransistors, the source 35 has its negative terminal connectedto thesupply connection 22 and its posisupply connection 21 being arbitrarilyconnected to a suitable reference potential, illustrated as circuitground by the con-.

ventional symbol. it should be apparent that when PNP-type transistorsare utilized in the current mode switching circuit, the polarity of'thesource would be reversed.

The binary signals A and B and the output signals C and C t have thewell-known form of H1 and LO voltage levels with transitionstherebetween as illustrated by the waveform 36 at the base electrode31b.

The fixed reference voltage V may be derived from any suitable source.By way of example, V could be obtained by means of a temperaturecompensated voltage divider arrangement connected between supplyconnections 21 and 22. The

' respectively, such that the output signals C and reference voltage Vhas a value intermediate the HI and LO voltage levels V and V and, forthe purpose of the following description, is assumed to be midwaytherebetwcen or VNF Q (1) A The output tenninals 25 and 26 are shown asconnected to loads, illustrated as capacitors C and C The capacitors Cand C represent the total input capacitance of the input transistors ofone or more other driven CML gates and also any other capacitance, suchas wiring capacitance, which may be present at the output terminals 25and 26.

OPERATION Consider now the circuit operation without regard to the loadcurrent switching transistors 13 and 14, and assume that transistors 15and 16 operate as emitter followers having separate series emitterresistors. The common emitter resistor 19 and the voltage source 35simulate a source of current for the current switching transistors 11and 12. When either or both of the A and B signals is at the H1 voltagelevel V (V,, V,,,), the transistor 11 and/or 31, as the case may be, isturned on and the transistor 12 is turned off. The current sourcecurrent is routed through the collector-emitter path of transistor 11and/or 31, as the case may be, with the result that the voltage at thecollector electrode lie is at a relatively low level; while the voltageat collector electrode 120 is at a relatively higher level. Theserelatively low and high voltage levels are translated with level shiftby the base-emitter junctions of transistors 15 and 16 to the outputterminals 25 and 26,

U are at the L and HI levels, respectively.

On the other hand,'when both of the binary signals A and B are at the L0voltage level V (V V,,,), the transistors 11 and 31 are tunred off andthe transistor 12 is turned on. The current source current is routedthrough the collector-toemitter path of the transistor 12 with theresult that the voltage at the collector electrode 120 is at arelatively low level; while the voltage at collector electrode 110 is ata relatively higher level. These relatively high and low voltage levelsat collector electrodes 11c and 12c are translated with level shift bythe base-emitter junctions of emitter-follower transistors 15 and 16 tothe output terminals 25 and 26, respectively, such that the outputsignals C and C are at the HI and LO levels, respectively.

In summary, whenever either or both of the input signals A and B is atthe HI level, the output C is at the LO level. It is only when bothbinary input signals A and B are at the LO level that the output signalC is at the HI level. Of course, the output signal C is the complementof the output signal C in each of the above cases. If the binary symbols1 and 0 are assigned to the HI and LO levels, respectively, the circuitcan be said to function as a NOR gate with respect to the output signalC and as an OR gate with respect to the output signal C.

0n the other hand, if the binary symbols 1 and 0 are assigned to the L0and HI levels, respectively, the circuit can be said to function as aNAND gate with respect to the output signal C and as an AND gate withrespect to the output signal ("5.

In the prior art CML gates wherein emitter-follower transistors and 16had series-emitter resistors returned at their other ends to the source35, current flowed in both resistors under steady state conditions tocontribute about 67 percent of the totalpower dissipation of the gate.In the present invention under steady state conditions, the emittercurrent of only one of the dual emitter-follower transistors flowsthrough the common emitter resistor resulting in a 50 percent reductionof power dissipation in the emitter-follower circuits.

The common emitter resistor 20 and voltage source 35 simulate a furthersource of current for switching transistors 13 and 14 which respond tothe binary input signals A and B to route the current of this furthersource to either one or the other but not both of the emitter-followertransistors 15 and 16. In essence, the fixed reference voltage V isshifted in level by an amount equal to the voltage across thebaseemitter junction (v,,,.) of transistor 12 so that base electrode 14bis effectively connected to a fixed reference voltage of V,,,- V On theother hand, the input signals A and B are also level shifted V volts bythe transistors 11 and 31 so that the signal swing at base electrode 13bis between V V, and V V,,,,. Thus, when either transistor 11 or 31 isturned on (B or A at the HI level) and transistor 12 turned off,transistors 13 and 14 are likewise turned on and off, respectively. Forthe other condition where both A and B are at the LO level,

transistors 11, 31 and 13 are turned off and transistors 12 and 1 14 areturned on. Thus, depending upon the binary signal input conditions, oneof the transistors 13 and 14 is turned on to route the current of theresistor 20 and source 35 current source to the associatedemitter-follower output transistor and output terminal.

It should be noted that although transistor 13 may be turned off (A B VC V to isolate emitter-follower transistor 15 from common emitterresistor 20, the latter transistor is still conducting (l) to provide abase current path for the the base electrode 13b of transistor 13 tofollow the input signals A and B without significant delay. in addition,the isolating devices 23 and 24 isolate the base electrode 13b from thebase electrode 14b.

Although the invention has been illustrated with specific types ofcurrent sources, for example resistor 19 and voltage source 35, thecurrent source may take on other forms. For example, the resistor 19could be replaced by a transistor which is biased in the linear mode toprovide a substantially constant current.

While the present invention has been illustrated with bipolartransistors, the invention is not limited to amplifying devices of thistype. Other amplifying devices, such as field-effect transistors,inayalso be employed in the practice of my invention.

I claim:

1. A current mode logic circuit having an input-. si rent switch withdual output follower type for producing complementary output signals atfirs and second output terminals in response to binary input signals;

5 wherein the improvement comprises:

a common load current path; and

load current switch means responsive to one input signal condition toconnect the common load current path to said first output terminal andto disconnect it from said second output terminal and responsive to adifferent input signal condition to connect the common load current pathto said second output terr'r'iinal and to disconnect it from said firstoutput terminal.

2. In combination:

four transistors of the same conductivity type, each having a collector,emitter and base, the first and second being connectedemitter-to-collector to-forrn one output terminal, the third and fourthbeing connected emitter-tocollector to form a second output terminal,the first and third being connected collector-to-collector to fonn athird terminal and the second and fourth being connectedemitter-to-emitter to form a fourth terminal;

fifth and sixth transistors of the same type as the first fourtransistors the fifth connected at its collector to the base of thefirst transistor and at its emitter to the base of the of said fifth andsixth transistors, for conducting current inthe forward direction tosaid fifth andsixth transistors.

4. A current mode logic circuit comprising, in combination: first andsecond amplifying devices, the first having an input second transistor,and the sixth transistor being connected at its collector to the base ofthe third transistor and at its emitter to the base of the fourthtransistor;

current source means connected between said third and fourth terminalsand also between the emitter and collec- 5 terminal adapted to receive arelatively fixed potential tor of said fifth and sixth transistors forsupplying operatand the second having an input terminal adapted to ingcurrent to all six of said transistors, said current receive an inputsignal having eithera first value higher source means including a firstimpedance connected to than said fixed potential or a second value lowerthan said the emitter of said second and fourth transistors andservfixed potential, and the first and second devices also each i a theommo emitter l ad for id e ond d 10 having an output terminal, one suchterminal for producfourth transistors and including also a secondimpedance ing an output signal of one sense and the other suchterconnected to the emitters of said fifth and sixth transistors n l forproducing an output signal of other Sen and serving as the commonemitter load for said fifth and first and Second follower-type aplifying means both of sixth transistors; and 1 which are normallyforward biase d,,the first such means means for concurrently placing thetransistor in its gonconnecting the output terminal Of thc'first device(0 a first ducting state and the sixth in itsnonconducting state tocircuitoutput terminal and h coupling the Output render the econdtransistor conductive and terminal Of the second device to a secondcircuit output transistor nonconductive, the conduction of said secondPermiflal, Said yP P p fy m for P transistor coupling said currentsource means ,to said .one 8 p f jy P S1gnals Said circuit p outputterminal and the nonconduction of said fourth temlmals hal/mg either a 8transistor decoupling said current source means from said a relamfelyconstant m QQF second output terminal; and for reversing the conditionof "F F d a load F f. s responsive to 531d the fifth and sixthtransistors -for rendering the fourth p slgnalfi Colfnectmg t Q l' Pthat one transistor conductive and the secondnonconductive, the of thetwo ip tefmmalls 'Whlch a conduction of said fourth transistor couplingsaid current Value and dlscofmeftmg 13 a source means to' said secondoutput terminal and the nonf" 2 the two C'mmtPmPUt Fl wh'ch at Fconduction of said second transistor decoupling said cur- P for Speedmgthe dlschafge P clrcult rent source means from said one output terminal.P telfmma] output potenftlal 1S fanmg and for 3. The combination as setforth in claim 2,: further including Y loadmg f o Sam t q f m two diodesconnected at electrode to Said Second that circuit output terminal whosepotential rs rising. pedance and at the other electrode to therespective emitters

